Click to expand full text
MC10E143, MC100E143
5 V ECL 9‐Bit Hold Register
Description The MC10E/100E143 is a 9-bit holding register, designed with
byte-parity applications in mind. The E143 holds current data or loads new data, with the nine inputs D0 − D8 accepting parallel input data.
The SEL (Select) input pin is used to switch between the two modes of operation − HOLD and LOAD. Input data is accepted by the registers a set-up time before the positive going edge of CLK1 or CLK2. A HIGH on the Master Reset pin (MR) asynchronously resets all the registers to zero.
The 100 Series contains temperature compensation.
Features
• 700 MHz Min. Operating Frequency • 9-Bit for Byte-Parity Applications • Asynchronous Master Reset • Dual Clocks • PECL Mode Operating Range:
♦ VCC= 4.2 V to 5.
MC10E143 Datasheet
